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cy8c21345, CY8C22345, cy8c22545 psoc ? programmable system-on-chip? cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-43084 rev. *h revised march 16, 2009 features powerful harvard architecture processor: ? m8c processor speeds up to 24 mhz ? 8x8 multiply, 32-bit accumulate ? low power at high speed ? 3.0v to 5.25v operating voltage ? industrial temperature range: -40c to +85c advanced peripherals (psoc blocks) ? six analog type ?e? psoc blocks provide: ? single or dual 8-bit adc ? comparators (up to four) ? up to eight digital psoc blocks provide: ? 8 to 32-bit timers, counters, and pwms ? one shot, multi shot mode support in timers and pwms ? pwm with deadband support in one digital block ? shift register, crc, and prs modules ? full duplex uart ? multiple spi ? masters or slaves, variable data length support: 8, 9, ...,16-bit ? can be connected to all gpio pins ? complex peripherals by combining blocks ? shift function support for fsk detection ? powerful synchronize featur e support. analog module operations can be sy nchronized by digital blocks or external signals. high speed 10-bit sar adc with sample and hold optimized for embedded control precision, programmable clocking: ? internal 5% 24/48 mhz oscillator across the industrial temperature range ? high accuracy 24 mhz with opti onal 32 khz crystal and pll ? optional external oscillator, up to 24 mhz ? internal/external oscillator for watchdog and sleep flexible on-chip memory: ? up to 16k bytes flash program storage 50,000 erase/write cycles ? up to 1k byte sram data storage ? in-system serial programming (issp ? ) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash optimized capsense resource: ? two idac support up to 640 a source current to replace external resistor ? two dedicated clock resources for capsense: ? csd_clk: 1/2/4/8/16/32/ 128/256 derive from sysclk ? cnt_clk: 1/2/4/8 derive from csd_clk ? dedicated 16-bit timers/counters for capsense scanning ? support dual csd channels simultaneous scanning programmable pin configurations: ? 25 ma sink on all gpio ? pull up, pull down, high z, strong, or open drain drive modes on all gpio ? up to 38 analog inputs on gpio ? configurable interrupt on all gpio additional system resources: ? i 2 c ? slave, master, and multimaster to 400 khz, supports hardware addressing feature ? watchdog and sleep timers ? user configurable low voltage detection ? integrated supervisory circuit ? on-chip precision voltage reference ? supports rtc block into digital peripheral logic top level block diagram digital system digital block array dbc dbc dcc dcc row 1 dbc dbc dcc dcc row 2 sram 1k interrupt controller sleep and watchdog multiple clock sources (includes imo, ilo, pll, and eco) global digital interconnect global analog interconnect cpu core (m8c) srom flash 16k macs internal voltage ref. digital clocks por and lvd system resets system resources analog system analog ref analog input muxing(l,r) = port 2 port 1 port 0 analog drivers 10-bit sar adc port 3 port 4 psoc core i 2 c system bus cte cte analog block array cte cte sce sce capsense digital resource [+] feedback www..net
cy8c21345, CY8C22345, cy8c22545 document number: 001-43084 rev. *h page 2 of 27 psoc ? functional overview the psoc ? family consists of many on-chip controller devices. these devices are designed to replace multiple traditional mcu-based system components with one low cost single-chip programmable device. psoc devices include configurable blocks of analog and digital logic, and programmable interconnects. this architecture enables the user to create customized peripheral conf igurations that match the requirements of each individual application. additionally, a fast cpu, flash program memory, sram data memory, and configurable io are included in a range of convenient pinouts and packages. the psoc architecture, shown in figure 1 , consists of four main areas: psoc core, digital system, analog system, and system resources. configurable global busing allows the combining of all the device resources into a complete custom system. the psoc family can have up to five io ports connecting to the global digital and analog interconnects, providing access to eight digital blocks and six analog blocks. psoc core the psoc core is a powerful engine that supports a rich feature set. the core includes a cpu, me mory, clocks, and configurable gpio (general purpose io). the m8c cpu core is a powerful processor with speeds up to 24 mhz, providing a four mips 8-bit harvard architecture micro- processor. the cpu uses an in terrupt controller with 21 vectors, to simplify the programming of real time embedded events. program execution is timed an d protected using the included sleep and watch dog timers (wdt). memory encompasses 16 kb of flash for program storage, 1k bytes of sram for data storage, and up to 2 kb of eeprom emulated using the flash. program flash uses four protection levels on blocks of 64 bytes, allowing customized software ip protection. the psoc device incorporates flexible internal clock generators, including a 24 mhz imo (internal main oscillator). the 24 mhz imo can also be doubled to 48 mhz for use by the digital system. a low power 32 khz ilo (internal low speed oscillator) is provided for the sleep timer and wdt. if crystal accuracy is required, the eco (32.768 khz external crystal oscillator) is available for use as a real time clock (rtc), and can optionally generate a crystal-accurate 24 mhz system clock using a pll. the clocks, together with progra mmable clock dividers (as a system resource), provide the flexibility to integrate almost any timing requirement into the psoc device. psoc gpios provide connection to the cpu, digital, and analog resources of the device. each pin?s drive mode may be selected from eight options, allowing gr eat flexibility in external interfacing. every pin can also generate a system interrupt on high level, low level, and change from last read. digital system the digital system is composed of eight digital psoc blocks. each block is an 8-bit resource that may be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. figure 1. digital system block diagram digital peripheral configurations are: pwms (8 to 32-bit) pwms with dead band (8 to 32-bit) counters (8 to 32-bit) timers (8 to 32-bit) uart 8 bit with selectable parity (up to two) spi master and slave (up to two) shift register (1 to 32-bit) i2c slave and master (one available as a system resource) cyclical redundancy checker/generator (8 to 32-bit) irda (up to two) pseudo random sequence generators (8 to 32-bit) the digital blocks may be connected to any gpio through a series of global buses that can route any signal to any pin. the buses also allow for signal multiplexing and performing logic operations. this configurability frees your designs from the constraints of a fixed peripheral controller. digital blocks are provided in ro ws of four, where the number of blocks varies by psoc device fam ily. this provides a choice of system resources for your applic ation. family resources are shown in ta b l e 1 on page 3. digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 row input configuration row output configuration 8 8 8 row 0 dbc00 dbc01 dcc02 dcc03 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect port 2 port 1 port 0 port 4 port 3 dbc00 dbc01 dcc02 dcc03 row 1 row input configuration row output configuration [+] feedback www..net
cy8c21345, CY8C22345, cy8c22545 document number: 001-43084 rev. *h page 3 of 27 analog system the analog system consists of a 10-bit sar adc and six configurable blocks. the programmable 10-bit sar adc is an optimized adc that could be run up to 200 ksps with 1.5 lsb dnl and 2.5 lsb inl (true for v dd 3.0v and vref 3.0v). external filters are required on adc input channels for antialiasing. this ensures that any out-of-band content is not folded into the input signal band. reconfigurable analog resources allow creating complex analog signal flows. analog peripherals are very flexible and may be customized to support specific application requirements. some of the more common psoc analog functions (most available as user modules) are: analog-to-digital converters (single or dual, with 8-bit resolution) pin-to-pin comparator single ended comparators with absolute (1.3v) reference or 5-bit dac reference 1.3v reference (as a system resource) analog blocks are provided in columns of four, which include ct-e (continuous time) and sc-e (switched capacitor) blocks. these devices provide limited functionality type ?e? analog blocks. figure 2. analog system block diagram additional system resources system resources, some of wh ich are listed in the previous sections, provide additional capability useful to complete systems. additional resources include a mac, low voltage detection, and power on rese t. the merits of each system resource are: digital clock dividers provide three customizable clock frequencies for use in applications. the clocks may be routed to both the digital and analog systems. additional clocks can be generated using digital psoc blocks as clock dividers. additional digital resources and clocks optimized for csd. support ?rtc? block into digital peripheral logic. a multiply accumulate (mac) provides a fast 8-bit multiplier with 32-bit accumulate, to assist in both general math and digital filters. the i2c module provides 100 and 400 khz communication over two wires. slave, master, and multi-master modes are all supported. low voltage detection (lvd) interrupts can signal the application of falling voltage levels, while the advanced por (power on reset) circuit eliminates the need for a system supervisor. an internal 1.3v reference provides an absolute reference for the analog system, including adcs and dacs. psoc device characteristics depending on your psoc device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 3 analog blocks. the following tabl e lists the resources available for specific psoc device groups. table 1. psoc device characteristics ace01 block array array input configuration aci1[1:0] aci0[1:0] reference generators bandgap agnd ase10 interface to digital system m8c interface (address bus, data bus, etc.) analog reference 10 bit sar adc aci2[3:0] p0[0:7] ace00 ase11 aci1[1:0] aci1[1:0] amuxr amuxl ace11 ace10 psoc part number digital io digital rows digital blocks analog inputs analog outputs analog columns analog blocks cy8c29x66 up to 64 4 16 12 4 4 12 cy8c27x66 up to 44 2 8 12 4 4 12 cy8c27x43 up to 44 2 8 12 4 4 12 cy8c22x45 up to 38 2 8 10 0 4 6 a cy8c21x34 up to 28 1 4 28 0 2 4 a a. limited analog functionality . cy8c21345 up to 24 1 4 10 0 4 6 a cy8c24x23 up to 24 1 4 12 2 2 6 cy8c24x33 up to 26 1 4 12 2 2 4 [+] feedback www..net
cy8c21345, CY8C22345, cy8c22545 document number: 001-43084 rev. *h page 4 of 27 getting started the quickest way to understand psoc silicon is to read this data sheet and then use the psoc designer integrated development environment (ide). this data sh eet is an overview of the psoc integrated circuit and presents specific pin, register, and electrical specifications. for in depth information, along with detailed programming details, see the psoc programmable system-on-chip technical reference manual for cy8c28xxx psoc devices. for up-to-date ordering, packaging , and electrical specification information, see the latest psoc device data sheets on the web at www.cypress.com/psoc . application notes application notes are an excellent introduction to the wide variety of possible psoc designs. they are located here: www.cypress.com/psoc . select application notes under the documentation tab. development kits psoc development kits are available online from cypress at www.cypress.com/shop and through a growing number of regional and global distributors, which include arrow, avnet, digi-key, farnell, future electronics, and newark. training free psoc technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training . the training covers a wide variety of topics and skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to www.cypress.com/cypros . solutions library visit our growing library of solution focused designs at www.cypress.com/solutions . here you can find various appli- cation designs that include firmware and hardware design files that enable you to complete your designs quickly. technical support for assistance with technical issues, search knowledgebase articles and forums at www.cypress.com/support . if you cannot find an answer to your question, call technical support at 1-800-541-4736. development tools psoc designer is a microsoft ? windows-based, integrated development environment for the programmable system-on-chip (psoc) devices. the psoc designer ide runs on windows xp or windows vista. this system provides design database management by project, an integrated debugger with in-c ircuit emulator, in-system programming support, and built-in support for third-party assemblers and c compilers. psoc designer also supports c language compilers developed specifically for the devices in the psoc family. psoc designer software subsystems system-level view a drag-and-drop visual embedded system design environment based on psoc express. in the system level view you create a model of your system inputs, ou tputs, and communication inter- faces. you define when and how an output device changes state based upon any or all other syst em devices. based upon the design, psoc designer automatically selects one or more psoc programmable system-on-chip co ntrollers that match your system requirements. psoc designer generates all embedded code, then compiles and links it into a programming file for a specific psoc device. chip-level view the chip-level view is a more traditional integrated development environment (ide) based on psoc designer 4.4. choose a base device to work with and then select different onboard analog and digital components called user modules that use the psoc blocks. examples of user modu les are adcs, dacs, amplifiers, and filters. configure the us er modules for your chosen application and connect them to each other and to the proper pins. then generate your project. this prepopulates your project with apis and libraries that you can use to program your application. the device editor also supports easy development of multiple configurations and dynamic reconfiguration. dynamic configuration allows for changing configurations at run time. hybrid designs you can begin in the system-level view, allow it to choose and configure your user modules, routing, and gen erate code, then switch to the chip-level view to gain complete control over on-chip resources. all views of the project share a common code editor, builder, and common debug, emulation, and programming tools. [+] feedback www..net
cy8c21345, CY8C22345, cy8c22545 document number: 001-43084 rev. *h page 5 of 27 code generation tools psoc designer supports multiple third party c compilers and assemblers. the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. the choice is yours. assemblers. the assemblers allow a ssembly code to merge seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compilers. c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs for the psoc family devices. the optimizing c compilers provide all the features of c tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger the psoc designer debugger s ubsystem provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an inte rnal view of the psoc device. debugger commands allow the designer to read and program and read and write data memory, read and write io registers, read and write cpu registers, set and clear breakpoints, and provide program run, halt, and step control. the debugger also allows the designer to create a trace buffer of registers and memory locations of interest. online help system the online help system displays online, context- sensitive help for the user. designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer in getting started. in-circuit emulator a low cost, high functionality ice (in-circuit emulator) is available for development support. this hardware has the capability to program single devices. the emulator consists of a ba se unit that connects to the pc using a usb port. the base unit is universal and operates with all psoc devices. emulation pods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full speed (24 mhz) operation. designing with psoc designer the development process for the psoc device differs from that of a traditional fixed function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divid ends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variety of user-selectable functions. the psoc development process can be summarized in the following four steps: 1. select components 2. configure components 3. organize and connect 4. generate, verify, and debug select components both the system-level and chip-level views provide a library of prebuilt, pretested hardware peripheral components. in the system-level view, these components are called ?drivers? and correspond to inputs (a thermistor, for example), outputs (a brushless dc fan, for exampl e), communication interfaces (i 2 c-bus, for example), and the logic to control how they interact with one another (called valuators). in the chip-level view, the components are called ?user modules?. user modules make selecting and implementing peripheral devices simple, and come in analog, digital, and programmable system-on-chip varieties. configure components each of the components you select establishes the basic register settings that implement the selected function. they also provide parameters and properties that a llow you to tailor their precise configuration to your particular application. for example, a pulse width modulator (pwm) user module configures one or more digital psoc blocks, one for each 8 bits of resolution. the user module parameters permit you to establish the pulse width and duty cycle. configure the pa rameters and properties to correspond to your chosen application. enter values directly or by selecting values from drop down menus. both the system-level drivers a nd chip-level user modules are documented in data sheets that are viewed directly in the psoc designer. these data sheets explain the internal operation of the component and provide performance specifications. each data sheet describes the use of each user module parameter or driver property, and other information you may need to successfully implement your design. [+] feedback www..net
cy8c21345, CY8C22345, cy8c22545 document number: 001-43084 rev. *h page 6 of 27 organize and connect you can build signal chains at the chip level by interconnecting user modules to each other an d the io pins, or connect system level inputs, outputs, and communication interfaces to each other with valuator functions. in the system-level view, select ing a potentiometer driver to control a variable speed fan driver and setting up the valuators to control the fan speed based on input from the pot selects, places, routes, and configures a programmable gain amplifier (pga) to buffer the input from the potentiometer, an analog to digital converter (adc) to conv ert the potentiometer?s output to a digital signal, and a pwm to control the fan. in the chip-level view, perform t he selection, configuration, and routing so that you have complete control over the use of all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, perform the ?generate application? step. this causes psoc designer to generate source code that automatically configures the device to your specification and pr ovides the software for the system. both system-level and chip-level designs generate software based on your design. the chip-l evel design provides application programming interfaces (apis) with high level functions to control and respond to hardware events at run-time and interrupt service routines that you can adapt as needed. the system-level design also gen erates a c main() program that completely controls the chosen application and contains place- holders for custom code at st rategic positions allowing you to further refine the software without disrupting the generated code. a complete code development environment allows you to develop and customize your applications in c, assembly language, or both. the last step in the development process takes place inside the psoc designer?s debugger subsystem. the debugger downloads the hex image to the in -circuit emulator (ice) where it runs at full speed. debugger ca pabilities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint and watch-variable features, the debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. document conventions acronyms used the following table lists the acronyms that are used in this data sheet. units of measure a units of measure table is locat ed in the electrical specifications section. table 5 on page 9 lists all the abbreviations used to measure the psoc devices. numeric naming hexadecimal numbers are represented with all letters in uppercase with an appended lowercas e ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicat ed by an ?h? or ?b? are decimal. table 2. acronyms acronym description ac alternating current adc analog-to-digital converter api application programming interface cpu central processing unit ct continuous time dac digital-to-analog converter dc direct current eeprom electrically erasable programmable read-only memory fsr full scale range gpio general purpose io ice in-circuit emulator ide integrated development environment io input/output ipor imprecise power on reset lsb least significant bit lvd low voltage detect msb most significant bit pc program counter por power on reset ppor precision power on reset psoc? programmable system-on-chip pwm pulse width modulator ram random access memory rom read only memory sc switched capacitor smp switch mode pump [+] feedback www..net
cy8c21345, CY8C22345, cy8c22545 document number: 001-43084 rev. *h page 7 of 27 pinouts this psoc device family is available in a variety of packages t hat are listed in the following tables. every port pin (labeled with a ?p?) is capable of digital io. ho wever, vss, vdd, and xres are not capable of digital io. CY8C22345, cy8c21345 28-pin soic table 3. pin definitions pin no. type pin name description digital analog 1 io i, mr p0[7] integration capacitor for mr 2 io i, ml p0[5] integration capacitor for ml 3 io i, ml p0[3] 4 io i, ml p0[1] 5 io i, ml p2[7] to compare column 0 6 io ml p2[5] optional adc external vref 7 io ml p2[3] 8 io ml p2[1] 9 power vss ground connection 10 io ml p1[7] i2c serial clock (scl) 11 io ml p1[5] i2c serial data (sda) 12 io ml p1[3] 13 io ml p1[1]* i2c serial clock (scl), issp-sclk 14 power vss ground connection 15 io mr p1[0]* i2c serial clock (scl), issp-sdata 16 io mr p1[2] 17 io mr p1[4] optional external clock input (ext-clk) 18 io mr p1[6] 19 input xres active high pin reset with internal pull down 20 io mr p2[0] 21 io mr p2[2] 22 io mr p2[4] 23 io i, mr p2[6] to compare column 1 24 io i, mr p0[0] 25 io i, mr p0[2] 26 io i, mr p0[4] 27 io i, mr p0[6] 28 power vdd supply voltage legend : a = analog, i = input, o = output, m=analog mux input, mr= analog mux right input, ml= analog mux left input, * issp pin whic h is not hiz at por. ai, mr, p0[7] ai, ml, p0[5] ai, ml, p0[3] ai, ml, p0[1] ai, ml, p2[7] adc_ext_vref, ml, p2[5] ml, p2[3] ml, p2[1] vss i2c scl, ml, p1[7] i2c sda, ml, p1[5] ml, p1[3] i2c scl, ml, p1[1] vss vdd p0[6], mr, ai p0[4], mr, ai p0[2], mr, ai p0[0], mr, ai p2[6], mr, ai p2[4], mr p2[2], mr p2[0], mr xres p1[6], mr p1[4], mr, extclk p1[2], mr p1[0], mr, i2c sdata soic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 figure 3. pin diagram [+] feedback www..net
cy8c21345, CY8C22345, cy8c22545 document number: 001-43084 rev. *h page 8 of 27 cy8c22545 44-pin tqfp table 4. pin definitions pin no. type pin name description digital analog 1 io ml p2[5] optional adc external vref 2 io ml p2[3] 3 io ml p2[1] 4 power vdd supply voltage 5 io ml p4[5] 6 io ml p4[3] 7 io ml p4[1] 8 power vss ground connection 9 io ml p3[7] 10 io ml p3[5] 11 io ml p3[3] 12 io ml p3[1] 13 io ml p1[7] i2c serial clock (scl) 14 io ml p1[5] i2c serial data (sda) 15 io ml p1[3] 16 io ml p1[1]* crystal (xtalin), i2c serial clock (scl), tc sclk 17 power vss ground connection 18 io mr p1[0]* crystal (xtalout), i2c serial data (sda), tc sdata 19 io mr p1[2] 20 io mr p1[4] optional external clock input (extclk) 21 io mr p1[6] 22 io mr p3[0] 23 io mr p3[2] 24 io mr p3[4] 25 io mr p3[6] 26 input xres active high pin reset with internal pull down 27 io mr p4[0] 28 io mr p4[2] 29 io mr p4[4] 30 power vss ground connection 31 io mr p2[0] 32 io mr p2[2] 33 io mr p2[4] 34 io i, mr p2[6] to compare column 1 35 io i, mr p0[0] 36 io i, mr p0[2] 37 io i, mr p0[4] p2[7], ml, ai adc_ext_vref, ml, p2[5] ml, p2[3] ml, p2[1] vdd tqfp 12 13 17 18 14 15 16 1 2 3 4 5 6 7 8 24 23 31 30 29 28 27 26 42 41 39 38 37 36 35 34 p0[1], ml, ai p0[3], ml, ai p0[5], ml, ai p0[7], mr, ai vdd p0[6], mr, ai i2c scl, ml, p1[7] i2c sda, ml, p1[5] p2[0], mr p0[0], mr, ai xres mr, p1[6] ml, p1[3] i2c scl, xtalin, ml, p1[1] i2c sda, xtalout, mr, p1[0] mr, p1[2] extclk, mr, p1[4] vss p2[6], mr, ai p2[4], mr 11 10 9 19 20 21 22 25 32 33 40 43 44 ml, p4[5] ml, p4[3] ml, p4[1] ml, p3[7] ml, p3[5] ml, p3[1] ml, p3[3] mr, p3[0] p3[2], mr p3[4], mr p3[6], mr p4[0], mr p4[2], mr p4[4], mr vss p2[2], mr p0[2], mr, ai p0[4], mr, ai vss figure 4. pin diagram [+] feedback www..net
cy8c21345, CY8C22345, cy8c22545 document number: 001-43084 rev. *h page 9 of 27 register reference this section lists the registers of this psoc device family by mapping tables. for detailed register information, refer the psoc programmable system-on chip technical reference manual. register conventions abbreviations used the register conventions specific to this section are listed in the following table. register mapping tables the psoc device has a total register address space of 512 bytes. the register space is also referred to as io space and is broken into two parts. the xoi bit in the flag register determines which bank the user is currently in. when the xoi bit is set, the user is said to be in the ?extended? address space or the ?configuration? registers. note in the following register mapping tables, blank fields are reserved and must not be accessed. 38 io i, mr p0[6] 39 power vdd supply voltage 40 io i, mr p0[7] integrati on capacitor for mr 41 io i, ml p0[5] integration capacitor for ml 42 io i, ml p0[3] 43 io i, ml p0[1] 44 io i, ml p2[7] to compare column 0 legend : a = analog, i = input, o = output, m=analog mux input, mr= analog mux right input, ml= analog mux left input, * issp pin whic h is not hiz at por. table 4. pin definitions (continued) pin no. type pin name description digital analog table 5. abbreviations convention description rw read and write register or bit(s) r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific [+] feedback www..net
cy8c21345, CY8C22345, cy8c22545 document number: 001-43084 rev. *h page 10 of 27 table 6. register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw 40 # asc10cr0* 80* rw c0 rw prt0ie 01 rw 41 w 81 rw c1 rw prt0gs 02 rw 42 rw 82 rw c2 rw prt0dm2 03 rw 43 # 83 rw c3 rw prt1dr 04 rw 44 # asd11cr0* 84* rw c4 rw prt1ie 05 rw 45 w 85 rw c5 rw prt1gs 06 rw 46 rw 86 rw c6 rw prt1dm2 07 rw 47 # 87 rw c7 rw prt2dr 08 rw 48 # 88 rw pwmvref0 c8 # prt2ie 09 rw 49 w 89 rw pwmvref1 c9 # prt2gs 0a rw 4a rw 8a rw idac_mode ca rw prt2dm2 0b rw 4b # 8b rw pwm_src cb # prt3dr 0c rw 4c # 8c rw ts_cr0 cc rw prt3ie 0d rw 4d w 8d rw ts_cmph cd rw prt3gs 0e rw 4e rw 8e rw ts_cmpl ce rw prt3dm2 0f rw 4f # 8f rw ts_cr1 cf rw prt4dr 10 rw csd0_dr0_l 50 r 90 rw cur pp d0 rw prt4ie 11 rw csd0_dr1_l 51 w 91 rw stk_pp d1 rw prt4gs 12 rw csd0_cnt_l 52 r 92 rw prv pp d2 rw prt4dm2 13 rw csd0_cr0 53 # 93 rw idx_pp d3 rw 14 rw csd0_dr0_h 54 r 94 rw mvr_pp d4 rw 15 rw csd0_dr1_h 55 w 95 rw mvw_pp d5 rw 16 rw csd0_cnt_h 56 r 96 rw i2c 0 _cfg d6 rw 17 rw csd0_cr1 57 rw 97 rw i2c 0 _scr d7 # 18 rw csd1_dr0_l 58 r 98 rw i2c 0 _dr d8 rw 19 rw csd1_dr1_l 59 w 99 rw i2c 0 _mscr d9 # 1a rw csd1_cnt_l 5a r 9a rw int_clr0 da rw 1b rw csd1_cr0 5b # 9b rw int_clr1 db rw 1c rw csd1_dr0_h 5c r 9c rw int_clr 2 dc rw 1d rw csd1_dr1_h 5d w 9d rw int_clr 3 dd rw 1e rw csd1_cnt_h 5e r 9e rw int_msk3 de rw 1f rw csd_cr1 5f rw 9f rw int_msk 2 df rw dbc00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbc00dr1 21 w amux_cfg 61 rw a1 int_msk1 e1 rw dbc00dr2 22 rw pwm_cr 62 rw a2 int_vc e2 rc dbc00cr0 23 # arf_cr 63 rw a3 res_wdt e3 w dbc01dr0 24 # cmp_cr0 64 # a4 dec_dh e4 rw dbc01dr1 25 w asy_cr 65 # a5 dec_dl e5 rw dbc01dr2 26 rw cmp_cr1 66 rw a6 dec _cr0* e6 rw dbc01cr0 27 # 67 rw a7 dec_cr1* e7 rw dcc02dr0 28 # adc0_cr 68 # a8 w mul 0 _x e8 w dcc02dr1 29 w adc1_cr 69 # a9 w mul 0 _y e9 w dcc02dr2 2a rw sadc_dh 6a rw aa r mul 0 _dh ea r dcc02cr0 2b # sadc_dl 6b rw ab r mul 0 _dl eb r dcc03dr0 2c # tmp_dr0 6c rw ac rw acc0_dr1 ec rw dcc03dr1 2d w tmp_dr1 6d rw ad rw acc0_dr0 ed rw dcc03dr2 2e rw tmp_dr2 6e rw ae rw acc0_dr3 ee rw dcc03cr0 2f # tmp_dr3 6f rw af rw acc0_dr2 ef rw dbc10dr0 30 # 70 rw rdi0ri b0 rw cpu a f0 # dbc10dr1 31 w 71 rw rdi0syn b1 rw cpu_t1 f1 # dbc10dr2 32 rw acb00cr1* 72* rw rdi0is b2 rw cpu_t2 f2 # dbc10cr0 33 # acb00cr2* 73* rw rdi0lt0 b3 rw cpu_x f3 # dbc11dr0 34 # 74 rw rdi0lt1 b4 rw cpu pcl f4 # dbc11dr1 35 w 75 rw rdi0ro0 b5 rw cpu_pch f5 # dbc11dr2 36 rw acb01cr1* 76* rw rdi0ro1 b6 rw cpu_sp f6 # dbc11cr0 37 # acb01cr2* 77* rw rdi0dsm b7 rw cpu_f f7 i dcc12dr0 38 # 78 rw rdi1ri b8 rw cpu_tst0 f8 rw dcc12dr1 39 w 79 rw rdi1syn b9 rw cpu_tst1 f9 rw dcc12dr2 3a rw 7a rw rdi1is ba rw cpu_tst2 fa rw dcc12cr0 3b # 7b rw rdi1lt0 bb rw cpu tst3 fb # dcc13dr0 3c # 7c rw rdi1lt1 bc rw dac1_d fc rw shaded fields are reserved and must not be accessed . # access is bit specific. * has a different meaning. [+] feedback www..net
cy8c21345, CY8C22345, cy8c22545 document number: 001-43084 rev. *h page 11 of 27 dcc13dr1 3d w 7d rw rdi1ro0 bd rw dac0_d fd rw dcc13dr2 3e rw 7e rw rdi1ro1 be rw cpu_scr1 fe # dcc13cr0 3f # 7f rw rdi1dsm bf rw cpu_scr0 ff # table 6. register map bank 0 table: user space (continued) name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access shaded fields are reserved and must not be accessed . # access is bit specific. * has a different meaning. table 7. register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 0 rw 40 rw asc10cr0* 80* rw c0 rw prt0dm1 1 rw 41 rw 81 rw c1 rw prt0ic0 2 rw 42 rw 82 rw c2 rw prt0ic1 3 rw 43 83 rw c3 rw prt1dm0 4 rw 44 rw asd11cr0* 84* rw c4 rw prt1dm1 5 rw 45 rw 85 rw c5 rw prt1ic0 6 rw 46 rw 86 rw c6 rw prt1ic1 7 rw 47 87 rw c7 rw prt2dm0 8 rw 48 rw 88 rw c8 # prt2dm1 9 rw 49 rw 89 rw c9 rw prt2ic0 0a rw 4a rw 8a rw ca rw prt2ic1 0b rw 4b 8b rw cb rw prt3dm0 0c rw 4c rw 8c rw cc # prt3dm1 0d rw 4d rw 8d rw cd rw prt3ic0 0e rw 4e rw 8e rw ce rw prt3ic1 0f rw 4f 8f rw cf rw prt4dm0 10 rw cmp0cr1 50 rw 90 rw gdi_o_in d0 rw prt4dm1 11 rw cmp0cr2 51 rw 91 rw gdi_e_in d1 rw prt4ic0 12 rw 52 rw 92 rw gdi_o_ou d2 rw prt4ic1 13 rw vdac50cr0 53 rw 93 rw gdi_e_ou d3 rw 14 rw cmp1cr1 54 rw 94 rw d4 rw 15 rw cmp1cr2 55 rw 95 rw d5 rw 16 rw 56 rw 96 rw d6 rw 17 rw vdac51cr0 57 rw 97 rw d7 rw 18 rw cscmpcr0 58 # 98 rw mux_cr0 d8 rw 19 rw cscmpgoen 59 rw 99 rw mux_cr1 d9 rw 1a rw cslutcr0 5a rw 9a rw mux_cr2 da rw 1b rw cmpcolmux 5b rw 9b rw mux_cr3 db rw 1c rw cmppwmcr 5c rw 9c rw dac_cr1# dc rw 1d rw cmpfltcr 5d rw 9d rw osc_go_en dd rw 1e rw cmpclk1 5e rw 9e rw osc_cr4 de rw 1f rw cmpclk0 5f rw 9f rw osc_cr3 df rw dbc00fn 20 rw clk_cr0 60 rw gdi_o_in_cr a0 rw osc_cr0 e0 rw dbc00in 21 rw clk_cr1 61 rw gdi_e_in_cr a1 rw osc_cr1 e1 rw dbc00ou 22 rw abf_cr0 62 rw gdi_o_ou_cr a2 rw osc_cr2 e2 rw dbc00cr1 23 rw amd_cr0 63 rw gdi_e_ou_cr a3 rw vlt_cr e3 rw dbc01fn 24 rw cmp_go_en 64 rw rtc_h a4 rw vlt_cmp e4 r dbc01in 25 rw cmp_go_en1 65 rw rtc_m a5 rw adc0_tr* e5 rw dbc01ou 26 rw amd_cr1 66 rw rtc_s a6 rw adc1_tr* e6 rw dbc01cr1 27 rw alt_cr0 67 rw rtc_cr a7 rw v2bg_tr e7 rw dcc02fn 28 rw alt_cr1 68 rw sadc_cr0 a8 rw imo_tr e8 w dcc02in 29 rw clk_cr2 69 rw sadc_cr1 a9 rw ilo_tr e9 w dcc02ou 2a rw 6a rw sadc_cr2 aa rw bdg_tr ea rw dbc02cr1 2b rw clk_cr3 6b rw sadc_cr3trim ab rw eco_tr eb w dcc03fn 2c rw tmp_dr0 6c rw sadc_cr4 ac rw mux_cr4 ec rw dcc03in 2d rw tmp_dr1 6d rw i2c0_ad ad rw mux_cr5 ed rw dcc03ou 2e rw tmp_dr2 6e rw ae rw mux_cr6 ee rw dbc03cr1 2f rw tmp_dr3 6f rw af rw mux_cr7 ef rw dbc10fn 30 rw 70 rw rdi0ri b0 rw cpu a f0 # dbc10in 31 rw 71 rw rdi0syn b1 rw cpu_t1 f1 # dbc10ou 32 rw acb00cr1* 72 rw rdi0is b2 rw cpu_t2 f2 # dbc10cr1 33 rw acb00cr2* 73 rw rdi0lt0 b3 rw cpu_x f3 # shaded fields are reserved and must not be accessed. # access is bit specific. * has a different meaning. [+] feedback www..net
cy8c21345, CY8C22345, cy8c22545 document number: 001-43084 rev. *h page 12 of 27 dbc11fn 34 rw 74 rw rdi0lt1 b4 rw cpu_pcl f4 # dbc11in 35 rw 75 rw rdi0ro0 b5 rw cpu_pch f5 # dbc11ou 36 rw acb01cr1* 76* rw rdi0ro1 b6 rw cpu_sp f6 # dbc11cr1 37 rw acb01cr2* 77* rw rdi0dsm b7 rw cpu_f f7 i dcc12fn 38 rw 78 rw rdi1ri b8 rw fls_pr0 f8 rw dcc12in 39 rw 79 rw rdi1syn b9 rw fls tr f9 w dcc12ou 3a rw 7a rw rdi1is ba rw fls_pr1 fa rw dbc12cr1 3b rw 7b rw rdi1lt0 bb rw fb dcc13fn 3c rw 7c rw rdi1lt1 bc rw fac_cr0 fc sw dcc13in 3d rw 7d rw rdi1ro0 bd rw dac_cr0# fd rw dcc13ou 3e rw 7e rw rdi1ro1 be rw cpu_scr1 fe # dbc13cr1 3f rw 7f rw rdi1dsm bf rw cpu_scr0 ff # table 7. register map bank 1 table: configuration space (continued) name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access shaded fields are reserved and must not be accessed. # access is bit specific. * has a different meaning. [+] feedback www..net
cy8c21345, CY8C22345, cy8c22545 document number: 001-43084 rev. *h page 13 of 27 electrical specifications this section presents the dc and ac electrical specifications of this psoc device family. for the latest electrical specificati ons, check the most recent data sheet by visiting the web at http://www.cypre ss.com/psoc. specifications are valid for -40c t a 85c and t j 100c, except where noted . specifications for devi ces running at greater than 12 mhz are valid for -40c t a 70c and t j 82c. figure 5. voltage versus operating frequency the following table lists the units of me asure that are used in this section. table 8. units of measure 5.25 4.75 3.00 93 khz 12 mhz 24 mhz cpu frequency vdd voltage v a l i d o pe r a t i n g r e gi o n symbol unit of measure symbol unit of measure c degree celsius w micro watts db decibels ma milli-ampere ff femto farad ms milli-second hz hertz mv milli-volts kb 1024 bytes na nano ampere kbit 1024 bits ns nanosecond khz kilohertz nv nanovolts k kilohm w ohm mhz megahertz pa pico ampere m megaohm pf pico farad a micro ampere pp peak-to-peak f micro farad ppm parts per million h micro henry ps picosecond s microsecond sps samples per second v micro volts s sigma: one standard deviation vrms micro volts root-mean-square v volts [+] feedback www..net
cy8c21345, CY8C22345, cy8c22545 document number: 001-43084 rev. *h page 14 of 27 absolute maximum ratings exceeding maximum ratings may shorten the useful li fe of the device. user guidelines are not tested. operating temperature table 9. absolute maximum ratings symbol description min typ max units notes t stg storage temperature -55 ? +100 c higher storage temperatures reduce data retention time t a ambient temperature with power applied -40 ? +85 c vdd supply voltage on vdd relative to vss -0.5 ? +6.0 v v io dc input voltage vss - 0.5 ? vdd + 0.5 v v ioz dc voltage applied to tristate vss - 0.5 ? vdd + 0.5 v i mio maximum current into any port pin -25 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd lu latch up current ? ? 200 ma table 10. operating temperature symbol description min typ max units notes t a ambient temperature -40 ? +85 c t j junction temperature -40 ? +100 c the temperature rise from ambient to junction is package specific. see table 31 on page 25. the user must limit the power consumption to comply with this requirement. [+] feedback www..net
cy8c21345, CY8C22345, cy8c22545 document number: 001-43084 rev. *h page 15 of 27 dc electrical characteristics dc chip level specifications ta b l e 11 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c, and are for design guidance only, unless specified otherwise. dc general purpose io specifications ta b l e 1 2 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only, unless otherwise specified. table 11. dc chip level specifications symbol description min typ max units notes vdd supply voltage 3.0 ? 5.25 v see table 18 on page 17 i dd supply current ? 7 12 ma conditions are vdd = 5.0v, 25c, cpu = 3 mhz, 48 mhz disabled. vc1 = 1.5 mhz vc2 = 93.75 khz vc3 = 93.75 khz i dd3 supply current ? 4 7 ma conditions are vdd = 3.3v t a = 25c, cpu = 3 mhz 48 mhz = disabled vc1 = 1.5 mhz, vc2 = 93.75 khz vc3 = 93.75 khz i sb sleep (mode) current with por, lvd, sleep timer, and wdt a a. standby current includes all functions (p or, lvd, wdt, sleep time) needed for reliable system operation. this must be compare d with devices th at have similar functions enabled. ? 3 6.5 a conditions are with internal slow speed oscillator, vdd = 3.3v -40c <= t a <= 55c i sbh sleep (mode) current with por, lvd, sleep timer, and wdt at high temperature a ? 4 25 a conditions are with internal slow speed oscillator, vdd = 3.3v 55c < t a <= 85c i sbxtl sleep (mode) current with por, lvd, sleep timer, wdt, and external crystal a ? 4 7.5 a conditions are with properly loaded, 1 w max, 32.768 khz crystal. vdd = 3.3v, -40c <= t a <= 55c i sbxtlh sleep (mode) current with por, lvd, sleep timer, wdt, and external crystal at high temperature a ? 5 26 a conditions are with properly loaded, 1 w max, 32.768 khz crystal. vdd = 3.3 v, 55c < t a <= 85c v ref reference voltage (bandgap) 1.275 1.3 1.325 v trimmed for appropriate vdd table 12. dc gpio specifications symbol description min typ max units notes r pu pull up resistor 4 5.6 8 k r pd pull down resistor 4 5.6 8 k v oh high output level vdd - 1.0 ? ? v ioh = 10 ma, vdd = 4.75 to 5.25v (80 ma maximum combined ioh budget) v ol low output level ? ? 0.75 v iol = 25 ma, vdd = 4.75 to 5.25v (100 ma maximum combined iol budget) v il input low level ? ? 0.8 v vdd = 3.0 to 5.25 v ih input high level 2.1 ? v vdd = 3.0 to 5.25 [+] feedback www..net
cy8c21345, CY8C22345, cy8c22545 document number: 001-43084 rev. *h page 16 of 27 dc operational amplifier specifications the following tables list the guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75v to 5. 25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c respectively. typical parameters apply to 5v or 3.3v at 25 c and are for design guidance only. dc low power comparator specifications ta b l e 1 5 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c respectively. typical parameters apply to 5v at 25 c and are for design guidance only. v h input hysterisis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. temp = 25c c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. temp = 25c table 12. dc gpio specifications (continued) symbol description min typ max units notes table 13. 5v dc operatio nal amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absol ute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/c i eboa a a. atypical behavior: i eboa of port 0 pin 0 is below 1 na at 25c; 50 na over temperat ure. use port 0 pins 1-7 for the lowest leakage of 200 na. input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25c v cmoa common mode voltage range 0.0 ? vdd - 1 v table 14. 3.3v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/c i eboa a input leakage current (port 0 anal og pins) ? 200 ? pa gross tested to 1 a c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 c v cmoa common mode voltage range 0 ? vdd - 1 v a.atypical behavior: i eboa of port 0 pin 0 is below 1 na at 25c; 50 na over temper ature. use port 0 pins 1-7 for the lowest leakage of 200 na. table 15. dc low power comparator specifications symbol description min typ max units v reflpc low power comparator (lpc) reference voltage range 0.2 ? vdd - 1 v v oslpc lpc voltage offset ? 2.5 30 mv [+] feedback www..net
cy8c21345, CY8C22345, cy8c22545 document number: 001-43084 rev. *h page 17 of 27 sar10 adc dc specifications ta b l e 1 6 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v or 3.3v at 25 c and are for design guidance only. dc analog mux bus specifications ta b l e 1 7 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v or 3.3v at 25 c and are for design guidance only. dc por and lvd specifications ta b l e 1 8 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v or 3.3v at 25 c and are for design guidance only. table 16. sar10 adc dc specifications symbol description min typ max units notes v adcvref reference voltage at pin p2[5] when configured as adc reference voltage 3.0 ? 5.25 v when v ref is buffered inside adc, the voltage level at p2[5] (when configured as adc reference voltage) must be always maintained to be at least 300 mv less than the chip supply voltage level on vdd pin. (v adcvref < vdd) i adcvref current when p2[5] is configured as adc v ref - ? 0.5 ma disables the internal voltage reference buffer inl at 10 bits integral nonlinearity -2.5 ?2.5lsbfor v dd 3.0v and vref 3.0v -5.0 ?5.0lsbfor v dd < 3.0v or vref < 3.0v dnl at 10 bits differential nonlinearity -1.5 ?1.5lsbfor v dd 3.0v and vref 3.0v -4.0 ?4.0lsbfor v dd < 3.0v or vref < 3.0v sps sample per second ? ? 150 ksps resolution 10 bits table 17. dc analog mux bus specifications symbol description min typ max units notes r sw switch resistance to common analog bus ? ? 400 vdd 3.00 r gnd resistance of initialization switch to gnd ? ? 800 table 18. dc por and lvd specifications symbol description min typ max units notes v ppor1 v ppor2 vdd value for ppor trip porlev[1:0] = 01b porlev[1:0] = 10b ?2.82 4.55 2.95 4.70 v v vdd must be greater than or equal to 3.0v during startup, reset from the xres pin, or reset from watchdog. v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 vdd value for lvd trip vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.95 3.06 4.37 4.50 4.62 4.71 3.02 3.13 4.48 4.64 4.73 4.81 3.09 3.20 4.55 4.75 4.83 4.95 v v v v v v [+] feedback www..net
cy8c21345, CY8C22345, cy8c22545 document number: 001-43084 rev. *h page 18 of 27 dc programming specifications ta b l e 1 9 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v or 3.3v at 25 c and are for design guidance only. table 19. dc programming specifications symbol description min typ max units notes vdd iwrite supply voltage for flash write operations 2.70 ? ? v i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.2 ? ? v i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull down resistor i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull down resistor v olv output low voltage during programming or verify ? ? vss + 0.75 v v ohv output high voltage during programming or verify vdd - 1.0 ? vdd v flash enpb flash endurance (per block) 50,000 ? ? ? erase/write cycles per block flash ent flash endurance (total) a a. a maximum of 36 x 50,000 block endurance cycles is allowed. this may be balanced between operatio ns on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maxi mum cycles each (to limit the total number of cycles to 36x5 0,000 and that no single block ever sees more than 50,000 cycles). b for the full industrial range, the user must employ a temper ature sensor user module (flashtemp) and feed the result to the te mperature argument before writing. refer to the flash apis application note an2015 at http://www.cypress.com under application notes for more information. 1,800,000 ? ? ? erase/write cycles flash dr flash data retention 10 ? ? years [+] feedback www..net
cy8c21345, CY8C22345, cy8c22545 document number: 001-43084 rev. *h page 19 of 27 ac electrical characteristics ac chip level specifications the following tables list the guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75v to 5. 25v and -40 c t a 85 c or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v or 3.3v at 25 c and are for design guidance only. figure 6. 24 mhz period jitter (imo) timing diagram figure 7. 32 khz period jitter (ilo) timing diagram table 20. 5v and 3.3v ac chip-level specifications symbol description min min(%) typ max max(%) units notes f imo24 internal main oscillator frequency for 24 mhz 22.8 24 25.2 a,b,c mhz trimmed for 5v or 3.3v operation using factory trim values. see figure 5 on page 13. slimo mode = 0 < 85 f imo6 internal main oscillator frequency for 6 mhz 5.75 8 6 6.35 a,b,c 8 mhz trimmed for 5v or 3.3v operation using factory trim values. see figure 5 on page 13. slimo mode = 0 < 85 f cpu1 cpu frequency (5v nominal) 0.93 24 24.6 a,b a. valid only for 4.75v < vdd < 5.25v. b. accuracy derived from internal main oscillator with appropriate trim for vdd range. mhz 24 mhz only for slimo mode = 0 f cpu2 cpu frequency (3.3v nominal) 0.93 12 12.3 b,c c. 3.0v < vdd < 3.6v. see application note an2012 ?adjusting psoc microcontroller trims for dual voltage-range operation? for information on trimming for opera- tion at 3.3v. mhz f blk5 digital psoc block frequency 0 (5v nominal) 0 48 49.2 a,b,d d. refer to the individual user module data sheets fo r information on maximum frequencies for user modules. mhz refer to table 25 on page 21. f blk33 digital psoc block frequency (3.3v nominal) 0 24 24.6 b,d mhz f 32k1 internal low speed oscillator frequency 15 32 75 khz f 32ku untrimmed internal low speed oscillator frequency 5 - - khz the ilo is not adjusted with the factory trim values until after the cpu starts running. see the ?system resets? section in the technical reference manual. jitter32k 32 khz rms period jitter ? 100 -- ns t xrst external reset pulse width 10 ? ? s dc24m 24 mhz duty cycle 40 50 60 % jitter24m1 24 mhz period jitter (imo) ? 300 600 ps f max maximum frequency of signal on row input or row output ? ? 12.3 mhz t ramp supply ramp time 25 ? ? s jitter24m1 f 24m jitter32k f 32k1 [+] feedback www..net
cy8c21345, CY8C22345, cy8c22545 document number: 001-43084 rev. *h page 20 of 27 ac general purpose io specifications ta b l e 2 1 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v or 3.3v at 25 c and are for design guidance only. figure 8. gpio timing diagram ac operational amplifier specifications ta b l e 2 2 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v or 3.3v at 25 c and are for design guidance only. ac low power comparator specifications ta b l e 2 3 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v at 25 c and are for design guidance only. ac analog mux bus specifications ta b l e 2 4 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v or 3.3v at 25 c and are for design guidance only. table 21. 5v and 3.3v ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns vdd = 4.5 to 5.25v, 10% - 90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns vdd = 4.5 to 5.25v, 10% - 90% trises rise time, slow strong mode, cload = 50 pf 7 27 ? ns vdd = 3 to 5.25v, 10% - 90% tfalls fall time, slow strong mode, cload = 50 pf 7 22 ? ns vdd = 3 to 5.25v, 10% - 90% tfallf tfalls tris ef trises 90% 10% gpio pin output voltage table 22. ac operational amplifier specifications symbol description min typ max units notes t comp comparator mode response time, 50 mv 100 ns vdd 3.0v table 23. ac low power comparator specifications symbol description min typ max units notes t rlpc lpc response time ? ? 50 s 50 mv overdrive comparator reference set within v reflpc table 24. ac analog mux bus specifications symbol description min typ max units notes f sw switch rate ? ? 3.17 mhz [+] feedback www..net
cy8c21345, CY8C22345, cy8c22545 document number: 001-43084 rev. *h page 21 of 27 ac digital block specifications the following tables list the guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75v to 5. 25v and -40 c t a 85 c or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v or 3.3v, at 25 c and are for design guidance only. ac external clock specifications the following tables list the guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75v to 5. 25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v or 3.3v at 25 c and are for design guidance only. table 25. 5v and 3.3v ac digital block specifications function description min typ max units notes all functions maximum block clocking frequency (> 4.75v) 49.2 mhz 4.75v < vdd < 5.25v maximum block clocking frequency (< 4.75v) 24.6 mhz 3.0v < vdd < 4.75v timer capture pulse width 50 a a. 50 ns minimum input pulse width is based on the input synchronizers running at 12 mhz (84 ns nominal period). ? ? ns maximum frequency, no capture ? ? 49.2 mhz 4.75v < vdd < 5.25v maximum frequency, with or without capture ? ? 24.6 mhz counter enable pulse width 50 ? ? ns maximum frequency, no enable input ? ? 49.2 mhz 4.75v < vdd < 5.25v maximum frequency, enable input ? ? 24.6 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 50 ? ? ns disable mode 50 ? ? ns maximum frequency ? ? 49.2 mhz 4.75v < vdd < 5.25v crcprs (prs mode) maximum input clock frequency ? ? 49.2 mhz 4.75v < vdd < 5.25v crcprs (crc mode) maximum input clock frequency ? ? 24.6 mhz spim maximum input clock frequency ? ? 8.2 mhz maximum data ra te at 4.1 mhz due to 2 x over clocking spis maximum input clock frequency ? ? 4.1 mhz width of ss_ negated between transmissions 50 ? ? ns transmitter maximum input clock frequency maximum input clock frequency with vdd 4.75v, 2 stop bits ? ? ? ? 24.6 49.2 mhz mhz maximum data rate at 3.08 mhz due to 8 x over clocking maximum data rate at 6.15 mhz due to 8 x over clocking receiver maximum input clock frequency maximum input clock frequency with vdd 4.75v, 2 stop bits ? ? ? ? 24.6 49.2 mhz mhz maximum data rate at 3.08 mhz due to 8 x over clocking maximum data rate at 6.15 mhz due to 8 x over clocking table 26. 5v ac external clock specifications symbol description min typ max units f oscext frequency 0.093 ? 24.6 mhz ? high period 20.6 ? 5300 ns ? low period 20.6 ? ?ns ? power up imo to switch 150 ? ? s [+] feedback www..net
cy8c21345, CY8C22345, cy8c22545 document number: 001-43084 rev. *h page 22 of 27 sar10 adc ac specifications ta b l e 2 8 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. ac programming specifications ta b l e 2 9 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v, or 3.3v at 25 c and are for design guidance only. table 27. 3.3v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 0.093 ? 12.3 mhz maximum cpu frequency is 12 mhz at 3.3v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. f oscext frequency with cpu clock divide by 2 or greater 0.186 ? 24.6 mhz if the frequency of the external clock is greater than 12 mhz, the cpu clock divider must be set to 2 or greater. in this case, the cpu clock divider ensures that the fifty percent duty cycle requirement is met. ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ?ns ? power up imo to switch 150 ? ? s table 28. sar10 adc ac specifications symbol description min typ max units freq 3 input clock frequency 3v ? ?2.7mhz freq 5 input clock frequency 5v ? ?2.7mhz table 29. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data set up time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz f sclk3 frequency of sclk3 0 ? 6 mhz v dd < 3.6v t eraseb flash erase time (block) ? 15 ? ms t write flash block write time ? 30 ? ms t dsclk data out delay from falling edge of sclk ? ? 55 ns 3.6 < vdd; at 30 pf load t dsclk3 data out delay from falling edge of sclk ? ? 65 ns 3.0 vdd 3.6; at 30 pf load [+] feedback www..net
cy8c21345, CY8C22345, cy8c22545 document number: 001-43084 rev. *h page 23 of 27 ac i 2 c specifications ta b l e 3 0 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, and 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. figure 9. definition for timing for fast/standard mode on the i 2 c bus table 30. ac characteristics of the i 2 c sda and scl pins for vdd 3.0v symbol description standard mode fast mode units min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? s t highi2c high period of the scl clock 4.0 ?0.6 ? s t sustai2c setup time for a repeated start condition 4.7 ?0.6 ? s t hddati2c data hold time 0 ?0 ? s t sudati2c data setup time 250 ?100 a a. a fast-mode i2c-bus device may be used in a standard-mode i2c-bus system, but the requirement t su;dat 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl si gnal. if such device does stretch the low period of the scl sig nal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i2c-bus specification) before the scl line is released. ?ns t sustoi2c setup time for stop condition 4.0 ?0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? s t spi2c pulse width of spikes are suppressed by the input filter ? ? 0 50 ns sda scl s sr s p t bufi2c t spi2c t hdstai2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c [+] feedback www..net
cy8c21345, CY8C22345, cy8c22545 document number: 001-43084 rev. *h page 24 of 27 packaging information this section provides the packaging specifications for this pso c device with the thermal impedanc es for each package, and the t ypical package capacitance on crystal pins. packaging dimensions figure 10. 28-pin soic figure 11. 44-pin tqfp 2. body length dimension does not include mold protrusion/end f lash,but mold protrusion/end flash shall not exceed 0.010 in (0.254 mm) per side does include mold mismatch and ar e measured at the mold parting line. pin 1 id 0.291[7.39] 0.300[7.62] 0.394[10.01] 0.419[10.64] 0.050[1.27] typ. 0.092[2.33] 0.105[2.67] 0.004[0.10] 0.0118[0.30] seating plane 0.0091[0.23] 0.0125[3.17] 0.015[0.38] 0.050[1.27] 0.013[0.33] 0.019[0.48] 0.026[0.66] 0.032[0.81] 0.697[17.70] 0.713[18.11] 0.004[0.10] 1 14 15 28 * * part # s28.3 standard pkg. sz28.3 lead free pkg. min. max. note : 1. jedec std ref mo-119 3. dimensions in inches 4. package weight 0.85gms 51-85026 *d 2. body length dimension does not include mold protrusion/end flash mold protrusion/end flash shall not exceed 0.0098 in (0.25 mm) per side body length dimensions are max plastic body size including mold mismatch 12.000.25 sq stand-off 0.600.15 121 r. 0.08 min. 0.20 min. 1.00 ref. 0 min. 0-7 0.20 max. 0.20 min. 0.25 (8x) gauge plane 10.000.10 sq 0.80 0.370.05 0.20 max. 0.05 min. 0.15 max. 44 1 1.60 max. 1.400.05 b.s.c. r. 0.08 min. seating plane see detail a detail a 11 33 23 12 22 34 0.10 note: 1. jedec std ref ms-026 3. dimensions in millimeters 51-85064 *c [+] feedback www..net
cy8c21345, CY8C22345, cy8c22545 document number: 001-43084 rev. *h page 25 of 27 thermal impedances capacitance on crystal pins ordering information the following table lists the key package features and ordering codes of this psoc device family. ordering code definitions table 31. thermal impedances per package package typical ja * 28 soic 68c/w 44 tqfp 61c/w * t j = t a + power x ja table 32. typical package capacitance on crystal pins package package capacitance 28 soic 2.7 pf 44 tqfp 2.6 pf table 33. psoc device family key features and ordering information package ordering code flash (kbytes) ram (bytes) temperature range digital blocks (rows of 4) analog blocks (columns of 3) digital io pins analog inputs analog outputs xres pin 28 soic cy8c21345-24sxi 8 512b -40c to +85c 4 6 24 10 0 y 28 soic CY8C22345-24sxi 16 1k -40c to +85c 8 6 24 10 0 y 44 tqfp cy8c22545-24axi 16 1k -40c to +85 c 8 6 38 10 0 y cy 8 c 2x xxx-spxx package type: thermal rating: p = pdip c = commercial s = soic i = industrial pv = ssop e = extended lf = mlf a = tqfp speed: 24 mhz part number family code (21, 22) technology code: c = cmos marketing code: 8 = cypress psoc company id: cy = cypress semiconductor [+] feedback www..net
cy8c21345, CY8C22345, cy8c22545 document number: 001-43084 rev. *h page 26 of 27 document history page document title: cy8c21345, CY8C22345, cy8c22545 psoc ? programmable system-on-chip? document number: 001-43084 revision ecn orig. of change submission date description of change ** 2251907 pmp/aesa see ec n new data sheet *a 2506377 eij/aesa see ecn changed data sheet stat us to ?preliminary?. changed part numbers to cy8c22x45. updated data sheet template. added 56-pin ocd information. added: ?y ou must put filters on intended adc input channels for anti-aliasing. this ensures that any out-of-band content is not folded into the input signal band." to section analog system on page 3. corrected minimum electro static discharge voltage in table 9 on page 14. *b 2558750 pmp/aesa 08/28/2008 updated features on page 1, psoc core on page 2, analog system on page 3. changed dbb to dbc, and dcb to dcc in register tables ta b l e 6 on page 10 and table 7 on page 11. removed inl at 8 bit reference in table 16 on page 17. changed idd3 value table 18 on page 17 typ:3.3 ma, max 6 ma added ?3.0v < vdd < 3.6v and -40c < t a < 85c, imo can guarantee 5% accuracy only? to table 20 on page 19. updated data sheet template. *c 2606793 nuq/aesa 11/19/2008 updated data sheet status to ?final?. updated block diagram on page 1. removed cy8c22045 56-pin ocd information. added part numbers cy8c21345, CY8C22345, and cy8c22545. for more details, see cdt 31271. *d 2615697 pmp/aesa 12/03/2008 confirmed CY8C22345 and cy8c21345 have same pinout on page 8. confirmed that imo has 5% accuracy in table 20 on page 19. *e 2631733 pmp/pyrs 01/07/2009 updated t able 16. sar10 adc dc specificatio ns and table 29 ac programming specifications. title changed to ?c y8c21345, CY8C22345, cy8c22545 psoc? programmable system-on-chip?? *f 2648800 jhu/aesa 01/28/2009 updated inl, dnl information in table 16 on page 17, development tools on page 4, and t dsclk parameter in table 29 on page 22. *g 2658078 hmi/aesa 02/11/2 009 updated section features on page 1. *h 2667311 jhu/aesa 03/16/2009 added parameter ?f 32ku ? and added min% and max % to parameter ?f imo6 ? in table 20 on page 19, according to updated slimo spec. [+] feedback www..net
document number: 001-43084 rev. *h revised march 16, 2009 page 27 of 27 psoc designer? and programmable system-on-chip? are trademarks and psoc? is a registered trademark of cypress semiconductor cor p. all other trademarks or registered trademarks referenced herein are property of the respective corporations. purchase of i2c components from cypress or one of its sublicensed associate d companies conveys a license under the philips i2c patent rights to use these components in an i2c system, provided that the system conforms to the i2c standard specification as defined by phi lips. all products and company names mentioned in this document may be the trademarks of their respective holders. cy8c21345, CY8C22345, cy8c22545 ? cypress semiconductor corporation, 2008-2009. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb [+] feedback www..net

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